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dc.contributor.advisorCarro, Luigipt_BR
dc.contributor.authorRutzig, Mateus Beckpt_BR
dc.date.accessioned2012-02-11T01:24:25Zpt_BR
dc.date.issued2012pt_BR
dc.identifier.urihttp://hdl.handle.net/10183/37178pt_BR
dc.description.abstractAs the number of embedded applications is increasing, the current strategy of several companies is to launch a new platform within short periods, to execute the application set more efficiently, with low energy consumption. However, for each new platform deployment, new tool chains must come along, with additional libraries, debuggers and compilers. This strategy implies in high hardware redesign costs, breaks binary compatibility and results in a high overhead in the software development process. Therefore, focusing on area savings, low energy consumption, binary compatibility maintenance and mainly software productivity improvement, we propose the exploitation of Custom Reconfigurable Arrays for Multiprocessor System (CReAMS). CReAMS is composed of multiple adaptive reconfigurable systems to efficiently explore Instruction and Thread Level Parallelism (ILP and TLP) at hardware level, in a totally transparent fashion. Conceived as homogeneous organization, CReAMS shows a reduction of 37% in energy-delay product (EDP) compared to an ordinary multiprocessing platform when assuming the same chip area. When a variety of processor with different capabilities on exploiting ILP are coupled in a single die, conceiving CReAMS as a heterogeneous organization, performance improvements of up to 57% and energy savings of up to 36% are showed in comparison with the homogenous platform. In addition, the efficiency of the adaptability provided by CReAMS is demonstrated in a comparison to a multiprocessing system composed of 4- issue Out-of-Order SparcV8 processors, 28% of performance improvements are shown considering a power budget scenario.en
dc.format.mimetypeapplication/pdfpt_BR
dc.language.isoengpt_BR
dc.rightsOpen Accessen
dc.subjectMultiprocessadorespt_BR
dc.subjectMultiprocessorsen
dc.subjectMicroeletrônicapt_BR
dc.subjectReconfigurable architecturesen
dc.subjectInstruction and thread level parallelismen
dc.subjectSistemas embarcadospt_BR
dc.titleA transparent and energy aware reconfigurable multiprocessor platform for efficient ILP and TLP exploitationpt_BR
dc.typeTesept_BR
dc.identifier.nrb000819304pt_BR
dc.degree.grantorUniversidade Federal do Rio Grande do Sulpt_BR
dc.degree.departmentInstituto de Informáticapt_BR
dc.degree.programPrograma de Pós-Graduação em Computaçãopt_BR
dc.degree.localPorto Alegre, BR-RSpt_BR
dc.degree.date2012pt_BR
dc.degree.leveldoutoradopt_BR


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