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dc.contributor.authorBrusamarello, Lucaspt_BR
dc.contributor.authorSilva, Roberto dapt_BR
dc.contributor.authorWirth, Gilson Inaciopt_BR
dc.contributor.authorReis, Ricardo Augusto da Luzpt_BR
dc.date.accessioned2011-01-29T06:00:41Zpt_BR
dc.date.issued2008pt_BR
dc.identifier.issn1057-7122pt_BR
dc.identifier.urihttp://hdl.handle.net/10183/27616pt_BR
dc.description.abstractIn deep-submicrometer technologies, process variability challenges the design of high yield integrated circuits. While device critical dimensions and threshold voltage shrink, leakage currents drastically increase, threatening the feasibility of reliable dynamic logic gates. Electrical level statistical characterization of this kind of gates is essential for yield analysis of the entire die. This work proposes a yield model for dynamic logic gates based on error propagation using numerical methods. We study delay and contention time in the presence of process variability. The methodology is employed for yield analysis of two typical wide-NOR circuits: one with a static keeper and another without the keeper. Since we use a general numerical approach for the calculation of derivatives and error propagation, the proposed yield analysis methodology may be applied to a wide range of dynamic gates (for instance pre-charge dynamic gates using dynamic keeper). The proposed methodology results in errors less than 2% when compared to Monte Carlo simulation, while increasing computational efficiency up to 100 .en
dc.format.mimetypeapplication/pdfpt_BR
dc.language.isoengpt_BR
dc.relation.ispartofIEEE transactions on circuits and systems. I, Regular Papers. New York. Vol. 55, no. 8 (Sept. 2008), p. 2238-2248pt_BR
dc.rightsOpen Accessen
dc.subjectDesign for yielden
dc.subjectMicroeletrônicapt_BR
dc.subjectMonte Carlo methodsen
dc.subjectProbabilistic analysisen
dc.subjectProcess variabilityen
dc.subjectVLSIen
dc.subjectYield estimationen
dc.titleProbabilistic approach for yield analysis of dynamic logic circuitspt_BR
dc.typeArtigo de periódicopt_BR
dc.identifier.nrb000684873pt_BR
dc.type.originEstrangeiropt_BR


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