Navegação Microeletrônica por Assunto "Leakage power minimization"
Resultados 1-1 de 1
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Tackling the drawbacks of a lagrangian relaxation based discrete gate sizing algorithm
(2018) [Dissertação]The shrink of the devices sizes allows the number of transistors in the integrated circuits to grow, leading to an increase in the leakage power. The discrete gate sizing technique consists in assigning each gate of the ...