Navegação Microeletrônica por Assunto "Lagrangian relaxation"
Resultados 1-3 de 3
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Cell selection to minimize power in high-performance industrial microprocessor designs
(2016) [Tese]This work addresses the gate sizing and Vt assignment problem for power, area and timing optimization in modern integrated circuits (IC). The proposed flow is applied to the Benchmark Suites of the International Symposium ... -
Discrete gate sizing and timing-driven detailed placement for the design of digital circuits
(2015) [Tese]Electronic design automation (EDA) tools play a fundamental role in the increasingly complexity of digital circuit designs. They empower designers to create circuits with several order of magnitude more components than it ... -
Tackling the drawbacks of a lagrangian relaxation based discrete gate sizing algorithm
(2018) [Dissertação]The shrink of the devices sizes allows the number of transistors in the integrated circuits to grow, leading to an increase in the leakage power. The discrete gate sizing technique consists in assigning each gate of the ...
