Navegação Microeletrônica por Assunto "EDA"
Resultados 1-7 de 7
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Boolean optimization of neural network circuits using signal probabilities and approximate computing through constant propagation
(2020) [Dissertação]The development of electronic devices has demonstrated amazing capabilities since the introduction of the transistor device. Humanity is more than ever, virtually connected. Information is at the grasp of most current human ... -
Cell selection to minimize power in high-performance industrial microprocessor designs
(2016) [Tese]This work addresses the gate sizing and Vt assignment problem for power, area and timing optimization in modern integrated circuits (IC). The proposed flow is applied to the Benchmark Suites of the International Symposium ... -
Discrete gate sizing and timing-driven detailed placement for the design of digital circuits
(2015) [Tese]Electronic design automation (EDA) tools play a fundamental role in the increasingly complexity of digital circuit designs. They empower designers to create circuits with several order of magnitude more components than it ... -
Finding placement-relevant clustersWith fast modularity-based clustering
(2020) [Tese]In advanced technology nodes, IC implementation faces an increasing design complexity as well as ever-more demanding design schedule requirements. This raises the need for new decomposition approaches that can help reduce ... -
Minimização lógica por fusão de portas
(2018) [Dissertação]Neste trabalho é apresentado um método para redução do número de transistores em circuitos integrados. Foram desenvolvidos um algoritmo e uma ferramenta de EDA baseada no mesmo, denominada de LOMGAM (Logic Minimization by ... -
Síntese automática do leiaute de redes de transistores
(2014) [Tese]Fluxo de síntese física baseado em standard cells tem sido utilizado na indústria e academia já há um longo período de tempo. Esta técnica é conhecida por ser bastante confiável e previsível uma vez que a mesma biblioteca ... -
Tackling the drawbacks of a lagrangian relaxation based discrete gate sizing algorithm
(2018) [Dissertação]The shrink of the devices sizes allows the number of transistors in the integrated circuits to grow, leading to an increase in the leakage power. The discrete gate sizing technique consists in assigning each gate of the ...
