Use of approximate triple modular redundancy for fault tolerance in digital circuits

Abstract

Triple Modular Redundancy (TMR) is a well-known mitigation technique, which provides a full masking capability to single faults, although at a great cost in terms of area and power consumption. For that reason, partial redundancy is often applied instead to alleviate these overheads. In this context, Approximate TMR, which is the implementation of TMR with approximate versions of the target circuit, has emerged in recent years as an alternative to partial replication, with the advantage of optimizing the trade-off between error coverage and area overhead. Several techniques for approximate circuit generation already exist in the literature, each one with its pros and con. This work do further study of the ATMR technique that evaluating the cost-benefit between area increase and coverage of approach failures. The first contribution is a new idea for the approximate-TMR approach where all of the redundant modules are approximate version of the original design, therefore allowing the creating o ATMR circuits with very low area overhead, we named this technique as Full-ATMR or just FATMR. The work also presents a novel approach for implementing approximate ATMR, in a automatic way, that combines an approximate gate library (ApxLib) with a Multi-Objective Optimization Genetic Algorithm (MOOGA). The algorithm performs a blind search, over the huge solution space, optimizing error coverage and area overhead altogether. Experiments compare our approach with a state of the art technique showing an improvement of trade-offs for different benchmark circuits. The last contribution is another novel approach to design ATMR circuits, it combines the idea of approximate library and heuristic. The approach uses testability and observability techniques in order to take decision on how to best approximate a circuit.