Mostrar registro simples

dc.contributor.advisorWirth, Gilson Inaciopt_BR
dc.contributor.authorRossetto, Alan Carlos Juniorpt_BR
dc.date.accessioned2018-12-06T02:45:54Zpt_BR
dc.date.issued2018pt_BR
dc.identifier.urihttp://hdl.handle.net/10183/186033pt_BR
dc.description.abstractThe complementary metal-oxide-semiconductor (CMOS) scaling process of the recent decades, coupled with new device structures and materials, has aggravated thermal problems and turned them into major reliability issues for deeply-scaled devices. As a consequence, the thermal transport dynamic and its impact on the device performance at submicron dimensions is established as a contemporary theme. In this context, a new selfconsistent electro-thermal particle-based device simulator for the study of self-heating effects in p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) based in silicon is developed and presented. The electrical module of the tool utilizes the Ensemble Monte Carlo method to perform the charge transport, whereas the thermal module evaluates the non-isothermal temperature profiles by solving the phonon energy balance equations for both acoustic and optical phonon baths. These temperature profiles are fed back into the electrical module, which adjusts the carriers’ scattering rate accordingly, thus, properly accounting for the device current capability degradation. The developed tool proved to be suitable for sub-100 nm device simulations, and it was used to perform relevant case study simulations of 24-nm channel length bulk and fully-depleted siliconon- insulator (FD-SOI) MOSFETs. General device parameters extracted from the simulations are qualitatively in agreement with the expected behavior, as well as data from the literature, ensuring the proper operation of the tool. Electro-thermal simulations of bulk and FD-SOI devices provided both acoustic and optical phonon temperature profiles across the transistor structure, as well as the heat generation map and the device power dissipation. Some results were also extracted via Joule heating thermal model, and they are presented for comparison. The current degradation due to self-heating was found to be significant for FD-SOI devices, but very modest for bulk ones. At a fixed bias point of VD =VG = 􀀀1:5 V, for instance, bulk devices presented a current variation of as much as 􀀀0:75%, whereas for FD-SOI devices it reached up to 􀀀8:82% for Tgate = 400 K. Hot spot acoustic (lattice) and optical phonon temperatures were extracted as a function of the applied bias for both topologies. The lattice temperature rise, for instance, exceeded 10 K and 150 K over the heat sink temperature for bulk and FD-SOI transistors, respectively, observing the same bias point and gate temperature presented earlier. The particle-based nature of the tool is also suitable for the study of the impact of trap activity in MOSFETs and its interplay with self-heating effects. Simulations of charge traps were used to analyze the statistical distribution of the current deviations in 25-nm bulk MOSFETs due to traps. The simulations showed that these deviations are exponentially-distributed, as experimentally observed and reported in the literature. Electro-thermal simulations of charge traps in bulk and FD-SOI transistors revealed that the largest degradation on the device current occurs when the effects of self-heating and trap activity take place simultaneously. At lower biases, the impact of charge traps dominates the current degradation, whereas the self-heating component prevails for larger biases.pt
dc.format.mimetypeapplication/pdfpt_BR
dc.language.isoengpt_BR
dc.rightsOpen Accessen
dc.subjectCMOSen
dc.subjectMicroeletrônicapt_BR
dc.subjectSelf-heatingen
dc.subjectSimulação computacionalpt_BR
dc.subjectReliabilityen
dc.subjectCmospt_BR
dc.subjectMOSFETen
dc.subjectMonte Carloen
dc.subjectCharge Trapsen
dc.titleModeling and simulation of self-heating effects in p-type MOS transistorspt_BR
dc.title.alternativeModelagem e simulação dos efeitos de auto aquecimento em transistores MOS do tipo P pt
dc.typeTesept_BR
dc.identifier.nrb001082280pt_BR
dc.degree.grantorUniversidade Federal do Rio Grande do Sulpt_BR
dc.degree.departmentInstituto de Informáticapt_BR
dc.degree.programPrograma de Pós-Graduação em Microeletrônicapt_BR
dc.degree.localPorto Alegre, BR-RSpt_BR
dc.degree.date2018pt_BR
dc.degree.leveldoutoradopt_BR


Thumbnail
   

Este item está licenciado na Creative Commons License

Mostrar registro simples