Motion estimation architecture using efficient adder-compressors for HDTV video coding

Abstract

This paper presents real time HDTV (High Definition Television) architecture for Motion Estimation(ME) using efficient adder compressors. The architecture is based on the Quarter Sub-sampledDiamond Search algorithm (QSDS) with Dynamic Iteration Control (DIC) algorithm. The main char-acteristic of the proposed architecture is the large amount of Processing Units (PUs) that are usedto calculate the SAD (Sum of Absolute Difference) metric. The internal structures of the PUs arecomposed by a large number of addition operations to calculate the SADs. In this paper, efficient 4-2 and 8-2 adder compressors are used in the PUs architecture to achieve the performance to workwith HDTV (High Definition Television) videos in real time at 30 frames per second. These addercompressors enable the simultaneous addition of 4 and 8 operands respectively. The PUs, usingadder compressors, were applied to the ME architecture. The implemented architecture wasdescribed in VHDL and synthesized to FPGA and, with Leonardo Spectrum tool, to the TSMC0.18μm CMOS standard cell technology. Synthesis results indicate that the new QSDS-DIC archi-tecture reach the best performance result and enable gains of 12% in terms of processing rate. Thearchitecture can reach real time for full HDTV (1920x1080 pixels) in the worst case processing 65frames per second, and it can process 269 HDTV frames per second in the average case.