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dc.contributor.advisorNão disponívelpt_BR
dc.contributor.authorBampi, Sergiopt_BR
dc.date.accessioned2009-12-31T04:14:59Zpt_BR
dc.date.issued1987pt_BR
dc.identifier.urihttp://hdl.handle.net/10183/17967pt_BR
dc.description.abstractReducing MOSFET dimensions while maintaining a constant supply voltage leads to higher electric fields inside the active regions of VLSI transistors. Operation of micron and submicron MOSFETs in the presence of high-field effects has required design innovations so that a constant supply voltage, acceptable punchthrough voltage, and long-term reliability are possible as device scaling continues. Drain engineering is necessary to cope with the susceptibility of MOSFETs to hot-carrier-related degradation. Reducing the electric fields at the drain end of the channel is critical to device reliability because degradation is related to carrier heating as they traverse regions with field strength in excess of 100 kV/cm. Optimized lightly doped drain (LDD) structures that spread the high electric field at the drain ensure the reliable 5 V operation of micron-sized n-channel MOSFETs. Recent experimental evidence revealed that LDDFETs are less reliable than conventional transistors if the n¯ region is too lightly doped. The JMOS transistor, a new n-MOS structure, is introduced to resolve the reliability problems in LDD devices with peak doping densities below 1 x 1018cm-³. A JFET is merged into the n-MOS structure to reduce the high fields under the gate. Two-dimensional simulations and experimental results demonstrate for the first time the operation of this device and its potential for VLSI applications requiring maximum supply voltage. A major experimental finding is that the JMOS can sustain 5 V operation even for submicron effective channel lengths because of the designer-controlled reduction of the maximum electrical field in the region under the gate traversed by carriers. The modification introduced in the LDD design is advantageous in terms of lower gate and substrate currents. Reliability can potentially be improved but at the expense of performance; however, the advantages of 5 V operation in micron-sized devices can outweigh this performance loss.en
dc.format.mimetypeapplication/pdfpt_BR
dc.language.isoengpt_BR
dc.rightsOpen Accessen
dc.subjectMicroeletrônicapt_BR
dc.titleA modified lightly doped drain mosfet for very large scale integrationpt_BR
dc.typeTesept_BR
dc.identifier.nrb000104774pt_BR
dc.degree.grantorStanford Universitypt_BR
dc.degree.localstanford, uspt_BR
dc.degree.date1987pt_BR
dc.degree.leveldoutoradopt_BR


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