Navegação Relatórios Técnicos e de Pesquisa por Assunto "Timing models"
Resultados 1-2 de 2
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Basic techniques of gate level simulation : a tutorial
(CPGCC da UFRGS, 1984) [Relatório Técnico e de Pesquisa]Gate level simulators are those which simulate digital logic circuits composed only of basic gates such as NAND's , NOR's, etc . There are two basic types of gate level simulators: compiled ones, in which the logic structure ... -
On the properties of event oriented logic simulation according to significant timing models
(CPGCC da UFRGS, 1985) [Relatório Técnico e de Pesquisa]This report discusses properties of event oriented logic simulators that employ the technique of selective searching the active gates. Properties of interest the data structures needed by are mainly related to data structures ...
