Now showing items 177-182 of 182

    • UFRGSPlace : a wirelength driven FPGA placement algorithm 

      Puget, Julia Casarin (2018) [Dissertation]
      FPGAs are semiconductor devices that can be reprogrammed to reach different application requirements after manufacturing. The architecture of an FPGA can be homogeneous, containing only standard blocks of an FPGA, IOs and ...
    • Use of approximate triple modular redundancy for fault tolerance in digital circuits 

      Gomes, Iuri Albandes Cunha (2018) [Thesis]
      Triple Modular Redundancy (TMR) is a well-known mitigation technique, which provides a full masking capability to single faults, although at a great cost in terms of area and power consumption. For that reason, partial ...
    • Utilizando folding no projeto de portas lógicas robustas à variabilidade de processo 

      Guex, Jerson Paulo (2013) [Dissertation]
      Este trabalho visa explorar técnicas de projeto de células que possibilitem a minimização dos efeitos da variabilidade de processo sobre o comportamento elétrico dos circuitos integrados. Para este trabalho foram abordados ...
    • Variability and voltage scaling aware FinFET design 

      Moraes, Leonardo Barlette de (2020) [Dissertation]
      Technology scaling alongside the increasing process variability impact in modern technology nodes are the main reasons to control deviations over metrics in IC nanometer designs. Also, given the increasing set of devices ...
    • VEasy : a tool suite towards the functional verification challenges 

      Pagliarini, Samuel Nascimento (2011) [Thesis]
      Esta dissertação descreve um conjunto de ferramentas, VEasy, o qual foi desenvolvido especificamente para auxiliar no processo de Verificação Funcional. VEasy contém quatro módulos principais, os quais realizam tarefas-chave ...
    • Voltage scaling interfaces for multi-voltage digital systems 

      Llanos, Roger Vicente Caputo (2015) [Dissertation]
      Multiple Voltage Digital Systems exploit the concept of voltage scaling by applying different supplies to particular regions of the chip. Each of those regions belongs to a power domain and may have two or more supply ...