A novel voltage-mode CMOS quaternary logic design

dc.contributor.author	Silva, Ricardo Cunha Gonçalves da	pt_BR
dc.contributor.author	Boudinov, Henri Ivanov	pt_BR
dc.contributor.author	Carro, Luigi	pt_BR
dc.date.accessioned	2011-01-28T05:59:11Z	pt_BR
dc.date.issued	2006	pt_BR
dc.identifier.issn	0018-9383	pt_BR
dc.identifier.uri	http://hdl.handle.net/10183/27584	pt_BR
dc.description.abstract	This brief presents a novel kind of voltage-mode CMOS design that uses multiple threshold voltage transistors and three power supply lines to implement quaternary logic gates, showing lower power dissipation and using less area than the present voltage-mode quaternary circuits. Inverter, NMIN, and NMAX gates are simulated with the Spice tool using TSMC 0.18-μm technology. The proposed logic circuits overcome the limitations of previous implementations used for multiple-valued logic circuits, such as static power consumption and noise vulnerability.	en
dc.format.mimetype	application/pdf	pt_BR
dc.language.iso	eng	pt_BR
dc.relation.ispartof	IEEE transactions on electron devices. New York. Vol. 53, n. 6 (June 2006), p. 1480-1483	pt_BR
dc.rights	Open Access	en
dc.subject	Inverter	en
dc.subject	Microeletrônica	pt_BR
dc.subject	Multiple-valued logic (MVL) circuits	en
dc.subject	NMAX	en
dc.subject	NMIN	en
dc.subject	Voltage-mode quaternary	en
dc.subject	CMOS desig	en
dc.title	A novel voltage-mode CMOS quaternary logic design	pt_BR
dc.type	Artigo de periódico	pt_BR
dc.identifier.nrb	000565276	pt_BR
dc.type.origin	Estrangeiro	pt_BR

This item is licensed under a Creative Commons License