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dc.contributor.authorGirardi, Alessandro Gonçalvespt_BR
dc.contributor.authorBampi, Sergiopt_BR
dc.date.accessioned2024-02-02T05:07:01Zpt_BR
dc.date.issued2007pt_BR
dc.identifier.issn1807-1953pt_BR
dc.identifier.urihttp://hdl.handle.net/10183/271397pt_BR
dc.description.abstractThis paper presents a transistor optimization methodology for low-power analog integrated CMOS circuits, relying on the physics-based gm/ID characteristics as a design optimization guide. Our custom layout tool LIT implements and uses the ACM MOS compact model in the optimization loop. The methodology is implemented for automation within LIT and exploits all design space through the simulated annealing optimization process, providing solutions close to optimum with a single technology-dependent curve and accurate expressions for transconductance and current valid in all operation regions. The compact model itself contributes to convergence and to optimized implementations, since it has analytic expressions which are continuous in all current regimes, including weak and moderate inversion. The advantage of constraining the optimization within a power budget is of great importance for low-power CMOS. As examples we show the optimization results obtained with LIT, resulting in significant power savings, for the design of a folded-cascode and a two-stage Miller operational amplifier.en
dc.format.mimetypeapplication/pdfpt_BR
dc.language.isoengpt_BR
dc.relation.ispartofJournal of integrated circuits and systems. Porto Alegre, RS. Vol. 2, n. 1 (Mar. 2007), p. 22-28pt_BR
dc.rightsOpen Accessen
dc.subjectAnalog designen
dc.subjectMicroeletrônicapt_BR
dc.subjectComputer-aided designen
dc.subjectSimulated annealingen
dc.titlePower constrained design optimization of analog circuits based on physical gm/ID characteristicspt_BR
dc.typeArtigo de periódicopt_BR
dc.identifier.nrb000608509pt_BR
dc.type.originNacionalpt_BR


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