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dc.contributor.authorMoratelli, Carlos Robertopt_BR
dc.contributor.authorCota, Erika Fernandespt_BR
dc.contributor.authorLubaszewski, Marcelo Soarespt_BR
dc.date.accessioned2024-02-02T05:04:49Zpt_BR
dc.date.issued2007pt_BR
dc.identifier.issn1807-1953pt_BR
dc.identifier.urihttp://hdl.handle.net/10183/271340pt_BR
dc.description.abstractThis work describes a hardware approach for the concurrent fault detection and error correction in a cryptographic core. It has been shown in the literature that transient faults injected in a cryptographic core can lead to the revelation of the encryption key using quite inexpensive equipments. This kind of attack is a real threat to tamper resistant devices like Smart Cards. To tackle such attacks, the cryptographic core must be immune to transient faults. In this work the DES algorithm is taken as a vulnerable cryptosystem case study. We show how an attack against DES is performed through a fault injection campaign. Then, a countermeasure based on partial hardware replication is proposed and applied to DES. Experimental results show the efficiency of the proposed scheme to protect DES against DFA fault attacks. Furthermore, the proposed solution is independent of implementation, and can be applied to other cryptographic algorithms, such as AES.en
dc.format.mimetypeapplication/pdfpt_BR
dc.language.isoengpt_BR
dc.relation.ispartofJournal of integrated circuits and systems. Porto Alegre, RS. Vol. 2, n. 1 (Mar. 2007), p. 14-21pt_BR
dc.rightsOpen Accessen
dc.subjectSmart ardsen
dc.subjectMicroeletrônicapt_BR
dc.subjectCryptographyen
dc.subjectFault attacksen
dc.subjectFault toleranceen
dc.titleA cryptography core tolerant to DFA fault attackspt_BR
dc.typeArtigo de periódicopt_BR
dc.identifier.nrb000608502pt_BR
dc.type.originNacionalpt_BR


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