Microeletrônica: Últimas Submissões
Resultados 71-80 de 218
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UFRGSPlace : a wirelength driven FPGA placement algorithm
(2018) [Dissertação]FPGAs are semiconductor devices that can be reprogrammed to reach different application requirements after manufacturing. The architecture of an FPGA can be homogeneous, containing only standard blocks of an FPGA, IOs and ... -
Exploring partial distortion elimination techniques in the sum of absolute differences architecture for HEVC integer motion estimation
(2019) [Dissertação]Digital videos are among the multimedia applications that have been given the most importance in the recent years, leading to the development of better compression techniques at the cost of higher computing requirements. ... -
Algorithms to improve area density utilization, routability and timing during detailed placement and legalization of VLSI circuits
(2019) [Tese]Placement is a challenging stage in the Very Large-Scale Integration (VLSI) physical design flow. In modern VLSI designs, several design restrictions have been imposed to address the complexity of advanced Complementary ... -
Design flow methodology for Radiation hardening by Design CMOS Enclosed Layout Transistor based standard cell library for aerospace applications
(2019) [Tese]Applications exposed to incidence of ionizing radiation, such as aerospace applications, may have their performance and reliability degraded by the interaction of high-energy ions. Thus, applications exposed to incidence ... -
Investigação dos processos de crescimento térmico de dióxido de silício sobre carbeto de silício
(2018) [Dissertação]Este trabalho investiga a cinética de oxidação do carbeto de silício (SiC) monocristalino, assim como as propriedades físico-químicas da interface e do filme fino de óxido (SiO2) formado. Serão discutidos filmes finos ... -
Parametric analysis and optimization of MOSFET macromodels for ESD circuit simulation
(2018) [Dissertação]Electrostatic discharge (ESD) is a major reliability concern in semiconductor industry. An ESD event may degrade or destroy an integrated circuit (IC), impacting on production yields, manufacturing costs, product quality, ... -
Tackling the drawbacks of a lagrangian relaxation based discrete gate sizing algorithm
(2018) [Dissertação]The shrink of the devices sizes allows the number of transistors in the integrated circuits to grow, leading to an increase in the leakage power. The discrete gate sizing technique consists in assigning each gate of the ... -
Avaliação de aspectos de projeto analógico usando enclosed layout transistors em tecnologia CMOS
(2018) [Tese]Este trabalho estuda o fluxo de projeto analógico com ferramentas de EDA (Electronic Design Automation) comerciais, adotando técnicas de proteção em nível de layout (RHBD – do inglês - Radiation Hardened-By-Design) através ... -
Use of approximate triple modular redundancy for fault tolerance in digital circuits
(2018) [Tese]Triple Modular Redundancy (TMR) is a well-known mitigation technique, which provides a full masking capability to single faults, although at a great cost in terms of area and power consumption. For that reason, partial ... -
Exact multi-level benchmark circuit generation for logic synthesis evaluation
(2018) [Dissertação]Electronic design automation (EDA) tools provide a highly automated flow for integrated circuit (IC) design. This flow may be roughly divided into three main steps: high-level synthesis, logic synthesis and physical ...